KembaraXtra-Case Law - The SR Latch

Definition

A latch is a basic memory element that stores one bit of data.

SR Latch Specifics

Inputs:

• S (Set): When activated (set to 1), forces the output Q to 1.
• R (Reset): When activated (set to 1), forces the output Q to 0.

Outputs:

• Q: The main output, representing the stored bit.
• Q̅: The inverse of Q. If Q is 1, then Q̅ is 0, and vice versa.

Behavior: Remembers the previous input state, acting as memory.

Truth Table (Operation of SR Latch)

Explanation:

• Hold (0,0): The latch maintains its previous state.
• Reset (0,1): The latch output Q is set to 0.
• Set (1,0): The latch output Q is set to 1.
• Invalid (1,1): Avoid this input combination, as the output is unpredictable.

Operation of NOR Gate

A NOR gate outputs 1 only when both inputs are 0. Otherwise, it outputs 0.

1. Initial State (S=0, R=1):

• R = 1 forces the output of NOR gate N2 (Q) to 0.
• Q = 0 is fed back into NOR gate N1.
• Since S = 0 and the other input to N1 is 0, the output Q becomes 1.
• The latch is in the reset state.
• [See Figure 6-3 in the original document]

2. Clear Inputs (S=0, R=0):

• R goes to 0.
• The output of N2 (Q) remains 0 because the other input to N1 is still 1.
• The latch remembers its previous state (reset).
• [See Figure 6-4 in the original document]

3. Activate S Input (S=1, R=0):

• S goes to 1.
• This forces the output of N1 (Q) to 0.
• Now, both inputs to N2 are 0, so the output of N2 (Q) becomes 1.
• The latch is now in the set state.
• [See Figure 6-5 in the original document]

4. Clear Inputs Again (S=0, R=0):

• S goes to 0.
• Q remains 1 because the other input to N1 is still 1.
• The latch remembers its previous state (set).
• [See Figure 6-6 in the original document]

Pulses

• The S and R inputs typically need to be pulsed rather than held high for a long period.
• This means quickly setting the input high and then back to low.
• When the circuit is at rest, both S and R are low.
• To change its state, just need to quickly set it high and then back to low—a simple pulse of the input.

Universal Logic Gates

• NOR gates (and NAND gates) are known as universal logic gates.
• This means that any other logic circuit can be created using only NOR gates (or only NAND gates).

Encapsulation

• The SR latch can be treated as a "black box" once its internal design is understood. This simplifies its use in larger circuits.
• Encapsulation allows us to focus on the function of the SR latch (1-bit memory) rather than its internal workings.