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KembaraXtra-Computer Science-Bus Communication
Introduction
Introduction
- Explains how the CPU communicates with memory and I/O devices.
- Focuses on the hardware communication system called a "bus."
- A hardware communication system used by computer components.
- Early buses were sets of parallel wires, each carrying an electrical signal (a bit).
- Modern buses can be more complex, but the core principle of data transfer remains.
- Address Bus:
- Selects the specific memory address the CPU wants to access.
- The CPU writes the desired memory address onto the address bus.
- Example: To access address 0x2FE, the CPU writes 0x2FE to the address bus.
- Data Bus:
- Transfers the actual data being read from or written to memory.
- For writing: The CPU writes the data to the data bus.
- For reading: The CPU reads the data from the data bus.
- Example: To write the value 25 to memory, the CPU writes 25 to the data bus.
- Control Bus:
- Manages and coordinates operations across the address and data buses.
- Carries signals indicating the type of operation (read or write).
- Indicates the status of an operation.
- Example: The CPU uses the control bus to signal a "write" operation.
- Scenario: The CPU wants to read the value at memory address 000003F4.
- Steps:
- The CPU writes 000003F4 to the address bus.
- The CPU sets a specific signal on the control bus to indicate a "read" operation.
- The memory controller (circuit managing memory interactions) receives these signals.
- The memory controller retrieves the data stored at address 000003F4 (which is 84 in the example).
- The memory controller writes the value 84 to the data bus.
- The CPU then reads the value 84 from the data bus.
- ddress space are mapped to I/O devices.
- The CPU communicates with the device by reading/writing to its assigned memory address(es).
- No special CPU instructions are needed for I/O.
- Port-Mapped I/O (PMIO):
- Devices are assigned an I/O port (a separate address space from memory).
- Special CPU instructions are used to access I/O devices via their port numbers.
- x86 CPUs support both MMIO and PMIO.
- Device Controllers:
- I/O ports and MMIO addresses generally refer to a device controller.
- The controller provides an interface for the CPU to request operations (read/write) on the device.
- The actual data on the device (e.g., bytes on a hard drive) is not directly mapped into address space.
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