TECHNOLOGY 

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KembaraXtra-Computer Science – CPU (Central Processing Unit)
I. Central Processing Unit (CPU) Fundamentals
A. Role of the CPU
  • Executes program instructions.
  • Enables computers to run diverse software.
  • Implements a specific set of instructions.
B. Types of CPU Instructions
  • Memory Access: Reading and writing data to memory.
  • Arithmetic: Performing calculations (add, subtract, multiply, divide, increment).
  • Logic: Executing logical operations (AND, OR, NOT).
  • Program Flow: Controlling the order of instruction execution (jump, call).
C. Program Execution
  • Programs are sequences of CPU instructions stored in memory.
  • The CPU fetches and executes these instructions in order.
  • Analogy: CPU is the cook, program is the recipe, instructions are the steps.
II. Instruction Set Architectures (ISAs)
A. ISA Definition
  • A family of CPUs that share the same instruction set.
  • Defines how a CPU works.
  • Software built for a specific ISA can run on any CPU implementing that ISA.
B. Prevalent ISAs
  • x86:
    • Dominant in desktops, laptops, and servers.
    • Originated with Intel's 8086 processor.
    • Includes processors from Intel and AMD.
    • Maintains backward compatibility (older software runs on newer CPUs).
    • Generations: 16-bit, 32-bit (IA-32), and 64-bit (x64 or x86-64).
  • ARM:
    • Predominant in mobile devices (smartphones, tablets).
    • Developed by ARM Holdings and licensed to manufacturers.
    • Often used in System-on-Chip (SoC) designs.
    • Known for low power consumption and cost.
    • Versions: 32-bit and 64-bit.
C. Processor Bitness (Word Size)
  • Refers to the number of bits a CPU can process at once.
  • Indicates the size of registers, address bus, and data bus.
  • Examples: 32-bit CPU, 64-bit CPU.
III. CPU Internals
A. Key Components
  • Processor Registers:
    • Internal storage locations for temporary data during processing.
    • Fast access but small capacity.
    • Implemented in the register file using SRAM.
  • Arithmetic Logic Unit (ALU):
    • Performs logical and mathematical operations.
    • Receives operands and an operation code as input.
    • Outputs the result and status.
  • Control Unit:
    • Directs the CPU, coordinating with registers, ALU, and memory.
    • Works in a repeating cycle: fetch, decode, execute.
    • Uses the program counter (PC) to track the memory address of the next instruction.
B. Fetch-Decode-Execute Cycle
  1. Fetch: Retrieve instruction from memory address indicated by the program counter (PC).
  2. Decode: Interpret the instruction.
  3. Execute: Perform the action specified by the instruction, using the ALU and registers as needed.
IV. Performance Enhancements
A. Clock Speed
  • Controls the rate at which the CPU transitions between states.
  • Measured in gigahertz (GHz).
  • Higher clock speed generally means more instructions per second.
  • Limited by heat generation and logic gate speed.
B. Multicore CPUs
  • CPUs with multiple processing units (cores).
  • Each core is an independent processor.
  • Enables parallel execution of instructions.
  • Software must be designed for parallelism to fully utilize multicore CPUs.
C. CPU Cache
  • Small amount of memory within the CPU that stores frequently accessed data.
  • Reduces the need to access main memory.
  • Levels: L1 (fastest, smallest), L2 (slower, larger), L3 (slowest, largest).
  • Can be core-specific (L1) or shared (L2, L3).
V. Key Terms
  • Instruction Set Architecture (ISA): The instruction set that a CPU family uses.
  • x86: A popular ISA used in most desktop computers.
  • ARM: A popular ISA used in most mobile devices.
  • Register: Small, fast storage location within the CPU.
  • ALU (Arithmetic Logic Unit): Performs arithmetic and logical operations.
  • Control Unit: Coordinates CPU operations.
  • Program Counter (PC): Holds the address of the next instruction to execute.
  • Clock Speed: The rate at which a CPU executes instructions (GHz).
  • Multicore: A CPU with multiple processing cores.
  • Cache: Small, fast memory within the CPU for frequently accessed data. L1, L2, and L3 are different levels of cache.



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